a non-disclosure agreement (nda ) is required for full disclosure of details . contact factory for more information. 1 of 3 rev: 061606 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channels. for information about ds5250 errata, contact the factory. general description the ds5250 is a highly secure, 4 clocks-per-machine cycle, 100% 8051-instruction-set-compatible microprocessor in the secure microcontroller family from dallas semiconductor. it was designed to be the cryptographic engine of pin pads, financial terminals, and any other application in which data security is paramount. a key feature of the device is that it encrypts its program memory with a hardware-based single or triple (3) des (data encryption standard) algorithm, making it nearly impossible to extract information. another des (3des) hardware block is available to the user for encrypting arbitrary information in data memory space. this makes the device ideal for storage and transmission of passwords, personal identification numbers, encryption keys, and other highly confidential information. applications pin pads financial terminals applications that require data security ordering information part temp range pin-package ds5250f-825 0c to +70c 80 plastic mqfp ds5250f-825+ 0c to +70c 80 plastic mqfp ds5250f-8n5 -40c to +85c 80 plastic mqfp ds5250f-8n5+ -40c to +85c 80 plastic mqfp DS5250F-125 0c to +70c 100 plastic mqfp DS5250F-125+ 0c to +70c 100 plastic mqfp ds5250f-1n5 -40c to +85c 100 plastic mqfp ds5250f-1n5+ -40c to +85c 100 plastic mqfp +denotes a lead-free/rohs-compliant package. note: all devices have a 25mhz maximum clock speed. features drop-in upgrade to the dallas ds5240 feature-rich, 8051-compatible, highly secure microcontroller accesses up to 4mb program and 4mb data memory (all nonvolatile) in-system programmable through serial port in-application programmable through user software; allows self-modification of program/data memory four 8-bit ports/one 6-bit port three 16-bit timer/counters 256 bytes of scratchpad ram advanced features crc-16/32 generator 5kb internal sram (optional 1kb stack) single or 3des engine partitionable memory segments variable from 4kb to 256kb high-speed architecture 4 clocks-per-machine cycle dc-to-25mhz operation single-cycle instruction in 160ns dual data pointers can increment or decrement independently automatic data pointer selection available programmable speed movx instructions 1kb on-chip instruction cache high-reliability operation power-fail/overvoltage reset early-warning powe r-fail interrupt watchdog timer nonvolatile functions on-chip real-time clock with alarm interrupt 2kb battery-backed internal sram security features designed to meet the physical security requirements of fips-140 and common criteria certifications program memory integrity checking executes single/3des-encrypted programs to prevent observation separate program/data cryptograph two self-destruct inputs 4096-bit modulo-arithmetic accelerator (maa) for pki operations built-in sensors detect attack and cause security response programmable attack countermeasures secure bootstrap loader true random-number generator (rng) unique id number in every device evaluation kit available (ds5250-kit) ds5250 high-speed secure microcontrolle r www.maxim-ic.com
a non-disclosure agreement (nda ) is required for full disclosure of details . contact factory for more information. ds5250 high-speed secure microcontroller 2 of 3 detailed description the ds5250 has a user-selectable, program memory integrit y-checking feature that triggers a tamper response if the decrypted program memory does not match a precalculated checksum, indicating a possible attack. in addition, all encryption keys for encrypted memory are stored in internal battery-backed sram so they can be erased instantaneously in the event tamper acti vity is detected. the battery-backed me mory architecture subjects critical application data and encryption keys stored internally to instantaneous zeroization, as defined in federal information processing standard (fips) 140-1 as a tamper response. additionally, power is removed from external memory, and all data and address lines are collapsed as an additional response to tamper detection. the ds5250 incorporates the most sophisticated security f eatures available in any microprocessor. the security features resist multiple levels of th reat, including observation, analysis, an d physical attack. attempts to discover the device?s encryption keys result in their erasure, rendering useless th e encrypted external memory. such measures require a massive effort to acquire any inform ation about the memory content s. sophisticated internal sensors monitor various environmental parameters, and trigge r a tamper response if they deviate from acceptable levels. a microprobe shield covers the top of the mi crocontroller die and deters tampering by triggering a destructive reset if it is breached. other security m easures implement defenses against known direct and side- channel attacks. specific security-related hardware incl udes a 4096-bit maa for public key infrastructure (pki) calculations, a random-number generator, a crc-16/ 32 generator, and a user-available des (or 3des) engine. in addition to the internal sensors, two external self-destr uct input (sdi) pins allow the designer to trigger a tamper response based on user-defined external stimuli. one sdi input controls destruction of program memory, external data memory, cache memory, key registers, and all the internal 5kb ram. the second sdi functions as an interrupt, allowing the application software to appropriatel y respond to a detected attack. other security methods include optional timed-access-write restrictions to t he parallel i/o port pins, making certain attack practices ineffective. program loading is accomplished using a secure rom-based serial port bootloader. the battery-backed nature of the ds5250, combined with an internal rom-based bootloader , allows frequent modification of secure information, either program or data, through a secure loading mechanis m. an optional challenge-response protection of access to the bootstrap-rom loader ensures that only trusted agents can load programs into the device. once the challenge response has been successfully complet ed, communications between the host system and the microcontroller are conducted in a 3des cipher-block-c hained data stream to prevent communication interception. alternatively, a user can create a custom bootload er using the microcontro ller?s encryption tools. pin configurations dallas semiconductor ds5250 mqfp 1 24 25 40 41 64 65 80 1 100 30 31 50 51 80 81 m q fp dallas semiconductor ds5250 top view
a non-disclosure agreement (nda ) is required for full disclosure of details . contact factory for more information. ds5250 high-speed secure microcontroller 3 of 3 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. figure 1. block diagram
|
